The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device including a plurality of memory cells.
The degree of the integration of a typical semiconductor memory device such as Double Data Rate Synchronous DRAM (DDR SDRAM) has been increasing significantly. Accordingly, one semiconductor memory device may include more than ten million memory cells. Such memory cells are regularly arranged and form a memory cell array. A group of memory cell arrays is referred to as a memory cell matrix (mat). A semiconductor memory device includes a plurality of memory cell matrixes.
Meanwhile, a memory cell structure of a semiconductor memory device is generally divided into a folded bit line structure and an open bit line structure.
The folded bit line structure typically includes a bit line sensing and amplifying unit, a bit line, and a bit line bar. The bit line sensing and amplifying unit is disposed at a core region of the semiconductor memory device. The bit line is used for driving data on the same memory cell matrix and the bit line bar is used as a reference for an amplification operation. The bit line and the bit line bar are arranged at the same memory cell matrix with respect the bit line sensing and amplifying unit. Therefore, the bit line and the bit line bar are affected by the same noise, and the generated noises are canceled by each other. The folded bit line structure guarantees stable operation over noise through the cancellation effect. Unlike the folded bit line structure, the open bit line structure includes a bit line and a bit line bar arranged at different memory cell matrixes with respect to the bit line sensing and amplifying unit. Therefore, noise generated from the bit line is different from noise generated from the bit line bar. As a result, the open bit line structure has a very low degree of noise tolerance.
The folded bit line structure includes a unit memory cell designed as 8F2, and the open bit line structure includes a unit memory cell designed as 6F2. Such a unit memory cell structure is a factor that decides a chip size of a semiconductor memory device. Based on the same data storage capacity, a semiconductor memory device having an open bit line structure may be designed to be smaller than a semiconductor memory device having a folded bit line structure.
FIG. 1 is a diagram illustrating a semiconductor memory device having an open bit line structure according to the related art.
Referring to FIG. 1, a semiconductor memory device according to the related art includes first and second memory cell matrixes having a plurality of memory cells arranged, a dummy matrix 105, and a plurality of sensing and amplifying units SA.
In general, the semiconductor memory device selects a memory cell corresponding to a row address and a column address in a read operation and outputs data stored in the selected memory cell. Here, the row address is used to activate one of a plurality of word lines WL and the column address is used to activate one bit of data amplified by the plurality of sensing and amplifying units SA.
Hereinafter, a read operation for reading data corresponding to a first bit line bar/BL1 will be described.
When a word line WL is activated in response to a row address for reading data corresponding to the first bit line bar/BL1, data stored in a memory cell connected to the activated word line WL is transferred to the plurality of sensing and amplifying units SA through a corresponding bit line. The plurality of sensing and amplifying units SA senses the transferred data and a reference voltage level which is a reference for sense amplification. Here, a sensing and amplifying unit 170A senses voltages of the first bit line bar/BL1 and the first bit line BL1 and performs an amplification operation. Here, the first bit line bar/BL1 is used to transfer data and the first bit line BL1 is used to transfer a reference voltage level. That is, the sensing and amplifying unit 170A senses and amplifies data transferred through the first bit line bar/BL1 using the first bit line and bit line bar BL1 and/BL1. Then, the sensing and amplifying unit 170A is selected by a column address, and the sense-amplified data is outputted.
Hereinafter, a read operation for reading data corresponding to a second bit line BL2 will be described.
When a word line WL is activated in response to a row address for reading data corresponding to the second bit line BL2, data stored in a memory cell connected to the selected word line WL is transferred to a sensing and amplifying unit SA through a corresponding bit line. A sensing and amplifying unit 170B senses voltages of a second bit line BL2 and a second bit line bar/BL2. That is, the second bit line BL2 is used to transfer data, and the second bit line bar/BL2 is used to transfer a voltage level which is a reference for a sensing and amplifying operation.
As described above, the semiconductor memory device according to the related art requires the dummy matrix 150 as a reference bit line to compare data of the second bit line BL2. The dummy matrix 150 includes the same load compared to that of the first memory cell matrix 110 and occupies the same amount of area as that occupied by the first cell matrix 110.
Thus, developing a semiconductor memory device having a comparatively small chip size by maximizing area efficiency by modifying an open bit line structure is desired.